1. Technical Field
The present invention relates to circuitry for an analog pseudo random bit sequence (PRBS) generator that can be used, for example, to exercise digital circuits using pseudo random patterns. The PRBS generator, in another example, can produce analog noise if fed into a digital circuit.
2. Related Art
FIG. 1 shows a block diagram of prior art digital implementation of a PRBS generator. This PRBS generator is used to exercise digital circuits using pseudo random bit patterns. It can also be used to produce analog noise if fed into a D/A converter. The circuit includes D-type flip-flops or registers 101-104 connected in series, and driven by a common clock signal Clk. Each of the registers 101-104 produces a respective tap output Q1-Q4. The Q1 tap from register 101 provides a first input to Exclusive OR (EXOR) gate 106. The Q4 tap produces a second input to the EXOR gate 106. The output D1 of EXOR gate 106 is provided back to the D input of the register 101. FIG. 2 provides a timing diagram showing the outputs from each of the taps Q1-Q4 and the EXOR gate 106 output D1 relative to the clock signal Clk.
FIG. 3 illustrates one alternative connection to FIG. 1 that produces the same pattern as shown in FIG. 2. FIG. 3 modifies FIG. 1 by including a register 301 with inputs connected in parallel with the register 101. The registers 101 and 301 receive a D input from the output of EXOR gate 106, while their clocks are provided by common clock Clk. The Q output of register 301 then matches the Q output of register 101 to produce the Q1 tap signal to an input of the EXOR gate 106.
The characteristics of the circuits of FIGS. 1 and 3 produce a random bit sequence that repeats every 2N-1 clock cycles. The all “0” state is prohibited, as this will “lock up” the generator. This state must be avoided at start-up. There are tables of tap connection vs. sequence length that are readily available from many sources. As an example, a 4 bit shift register making up a PRBS generator with an EXOR gate as shown in FIGS. 1 and 3 will produce a maximum length sequence of 24−1=15 state changes before repeating the sequence.
There is no inherent upper limit to the frequency of operation with the components of FIGS. 1 and 3, except that of the logic elements used. To reduce the expense for higher frequency PRBS generators, however, there are techniques that allow several lower frequency PRBS generators to be multiplexed to arrive at a higher frequency. The multiplexer is the only element that operates at the elevated frequency. The high frequency multiplexers can be made much more easily than D flip-flops and EXOR gates. The disadvantage of this technique is that the system can become very complex and expensive when system frequencies approach the 10's of GHz range. As an example Anritsu Company of Morgan Hill, Calif. manufactures a 12.5 GHz PRBS generator model MP1763B that sells for over $100,000.
It would be desirable to provide components for a PRBS generator that can operate at frequencies into the 10's of GHz range, while minimizing manufacturing costs.